The present invention relates to a method for forming a fine pattern of a semiconductor device, and more specifically, to preventing a defect generated from first and second mask processes in a double exposure process to overcome a resolution limit of an exposer.
As semiconductor devices become smaller and more highly-integrated, the chip area is increased in proportion to an increase of memory capacity, but an area of a cell region where a pattern of the semiconductor device is formed is decreased. Since more patterns are required in a limited cell region in order to secure a desired memory capacity, a critical dimension (CD) of the pattern is decreased so that the pattern becomes finer.
A lithography process is commonly used to obtain a pattern having a smaller CD. The lithography process includes: coating a photoresist over a substrate; exposing the photoresist with an exposure mask having a fine pattern by using a light source having a wavelength of 365 nm, 248 nm, 193 nm and 153 nm; and performing a development process to form a photoresist pattern that defines the fine pattern.
In the lithography process, the resolution (R) is determined depending on a wavelength (λ) and a numerical aperture (NA) of the light source as shown in the equation R=k1×λ/NA. In the equation, k1 is a process constant having a physical limit, so that it cannot be decreased by a general method. A new photoresist material having a high reactivity to short wavelengths is required with an exposer using the short wavelengths, so that it is difficult to form a fine pattern having a CD less than a short wavelength.
As a result, ‘a double patterning technology’ has been developed for overlapping patterns under consideration of an exposer to obtain a fine pattern.
The double patterning process includes forming a first hard mask over a semiconductor substrate. The first hard mask defines a CD three times larger than that of a fine pattern. A second hard mask is formed over the first hard mask such that it is aligned alternately with the first hard mask, thereby obtaining a fine pattern by the first and second hard masks. However, a process margin for aligning the first hard mask and the second hard mask accurately is decreased to reduce a margin of the double patterning process.
In order to prevent decrease of the margin, a sacrificial oxide pattern is formed, and a spacer is formed on sidewalls of the oxide pattern so that the spacer may be used as a hard mask that defines a fine pattern. Although the method for forming a fine pattern using the spacer may improve a process margin for forming a fine pattern, a dummy pattern also becomes smaller to generate a defect of the dummy pattern.
As mentioned above, in the conventional method for forming a fine pattern of a semiconductor device, it is difficult to form a fine pattern having a small CD due to limits of the resolution of the exposer. In the double exposure process for overcoming the limits, patterns may be misaligned in a mask forming process that is performed twice. Although a method for forming a fine pattern using a spacer is developed, a dummy pattern is also defined in a spacer hard mask forming process for forming a fine pattern. As a result, the dummy pattern is deteriorated, and yield and reliability of the semiconductor device is degraded.